The present invention generally relates to fabrication of semiconductor memory devices and more particularly to a method for fabricating a non-volatile semiconductor memory device having a floating gate electrode.
In relation to the storage device of computers, there is a continuous demand for a non-volatile semiconductor memory device having a large capacity for storing information. Particularly, the so-called flash-erasable EPROM or simply flash-EPROM has been studied intensively in recent years as an alternative of hard disk devices. In flash EPROMs, rewriting of data is possible similarly to the conventional random access memories, while the device can hold the written information even when the electrical power is turned off. Thus, the device is ideal for external storage device of computers such as hard disk. Further, application to the memory cards is studied. In relation to various applications of the flash-EPROM, intensive efforts are in progress to improve the reliability and life-time of the device as well as to reduce the cost of fabrication.
A flash-EPROM has a structure similar to the conventional MOS transistor and stores information in an insulated, floating gate in the form of electric charges. Particularly, the device called FLOTOX (floating gate, Tunnel Oxide) type or ETOX (EPROM Tunnel Oxide) type is characterized by a control gate provided on a floating gate with a separation therefrom by an capacitor insulation film. When writing information, hot electrons are injected into the floating gate electrode from a drain region formed in a semiconductor substrate via a gate insulation film located underneath the floating gate by the tunneling effect, wherein the tunneling effect is caused by applying a control voltage to the control electrode. Erasing of information, on the other hand, is carried out by causing a tunneling of electrons through the gate oxide film to dissipate the electrons into a source region also formed in the substrate. In order to facilitate the tunneling of electrons, the gate oxide film is formed to have a reduced thickness as compared with conventional MOS transistors.
In order to achieve an efficient control of the foregoing tunneling of electrons by the control gate, one has to secure a large ratio for the parameter C.sub.2 /(C.sub.1 +C.sub.2), wherein the term C.sub.1 represents the capacitance formed between the floating gate electrode and the semiconductor substrate, while the parameter C.sub.2 represents the capacitance that is formed between the floating gate electrode and the control gate electrode. The above requirement in turn imposes a requirement that the insulation film surrounding the floating gate be formed as thin as possible. Thereby, a process is required to form such an insulation film with improved quality. It will be noted that there should be no leak current flowing through the insulation film. In other words, it is critical to the successful operation of the flash-EPROM to form the insulation film that surrounds the floating gate as thin as possible and simultaneously with a high quality such that the insulation film is substantially free from impurities.
Conventionally, the flash-EPROM of the FLOTOX type has been fabricated according to the process shown in FIGS. 1(A)-1(I), wherein the device shown on the left side of the drawing represents the memory cell transistor in the cross sectional view taken along the gate-length direction (X-direction), while the device in the middle represents the same memory cell transistor taken in the gate-width direction (Y-direction). It should be noted that the memory cell transistor has a structure similar to a MOS transistor. On the other hand, the drawing shown on the right side represents a MOS transistor that is provided in a peripheral region as a peripheral device.
Referring to FIG. 1(A) at first, a field oxide film 2 is formed selectively on a silicon substrate 1 for device isolation by an oxidation process conducted in a wet O.sub.2 environment while protecting the device region, on which a memory cell transistor or a peripheral transistor is to be formed, by means of a mask such as silicon nitride not illustrated. After removing the mask, a silicon oxide film 3a is formed by an oxidation process conducted in a dry O.sub.2 environment, as a gate insulation film of the memory cell transistor to be formed in the memory cell region. Simultaneously, a silicon oxide film 3b is formed on the peripheral region.
Next, a first channel region 5a is formed as shown in FIG. 1(B) by an ion implantation process for controlling the threshold voltage of the MOS transistor forming the memory cell. Thereby, the peripheral region is masked with a photoresist 4, and the impurity element is injected selectively into the channel region via the gate insulation film 3a. It should be noted that the ion implantation of the impurity element should be conducted after the gate insulation film 3a is formed, as the thermal treatment associated with the formation of the gate insulation film 3a tends to cause a diffusion of the impurity elements into the interior of the substrate 1 or segregation of the impurity element at the interface between the gate insulation film 3a and the substrate 1, when the foregoing processes are reversed.
Next, a first polysilicon layer 6 is formed on the entire surface of the silicon substrate 1 as shown in FIG. 1(C), wherein it will be noted that the layer 6 forms the floating gate electrode of the flash-EPROM in the subsequent patterning process. Thus, in the step of FIG. 1(D), the first polysilicon layer 6 is patterned to form an isolated electrode pattern 6a corresponding to a gate electrode of the MOS transistor that forms the memory cell transistor. On the other hand, the first polysilicon layer 6 is removed from the peripheral region. Further, the memory cell region is protected by a resist 7 and the silicon oxide film 3b formed on the peripheral region is removed so that the Si substrate 1 is exposed.
Next, the photoresist 7 is removed and the structure of FIG. 1(D) is subjected to a thermal oxidation process conducted in a dry O.sub.2 environment such that the electrode 6a is covered by a silicon oxide film 8a that acts later on as a capacitor insulation film. Simultaneously, a silicon oxide film 8b is formed in the peripheral region as shown in FIG. 1(E) as a gate insulation film of the peripheral MOS transistor to be formed. Thereby, the gate electrode 6a is covered by silicon oxide for the entirety thereof and is insulated from the surrounding. In other words, the electrode 6a forms a floating gate of the flash-EPROM.
After the silicon oxide film 8a is formed as above, an ion implantation process is conducted again to form a second channel region 5b for controlling the threshold voltage of the peripheral MOS transistor as shown in FIG. 1(F). Here, it should be noted that the memory cell transistor including the capacitor insulation film 8a of the floating gate 6a is covered by a resist 9 such that no ion implantation occurs in the memory cell region.
Next, the resist 9 is removed and a second polysilicon layer 10 is deposited on the entirety of the surface of the substrate 1 including the memory cell region and the peripheral region as indicated in FIG. 1(G), and the polysilicon layer 10 thus deposited is patterned as shown in FIG. 1(H) by using a resist pattern 10.sub.1 as a mask to form a control electrode 10a located above the floating gate electrode 6a. Further, the polysilicon layer 10 is patterned by using a resist pattern 10.sub.2 as a mask to form a gate electrode 10b of the peripheral MOS transistor.
Next, an ion implantation process is achieved for incorporating the impurity element into the substrate 1 in correspondence to the source and drain of the memory cell transistor as well as in correspondence to the source and drain of the peripheral transistor according to the self alignment process that uses the floating electrode 6a and the control electrode 10a in the memory cell region and the gate electrode 10b in the peripheral region as a mask. Thereby, diffusion regions 12a and 12b are formed as the source and drain of the memory cell transistor. Further, diffusion regions 13a and 13b are formed as the source and drain of the peripheral transistor.
Further, an inter-layer insulation film 14 is deposited on the entirety of the structure thus formed, and contact holes 15a and 15b are formed at both sides of a gate structure 11a that includes the floating electrode 3a and the control electrode 10a buried under the insulation film 14, to expose the upper major surface of the diffusion regions 12a and 12b. Similarly, contact holes 16a and 16b are formed in the insulation film 14 at both sides of a gate structure 11b that in turn includes the gate electrode 10b covered by the insulation film 14, to expose the upper major surface of the diffusion regions 13a and 13b. Further, a polysilicon layer is deposited to fill the contact holes 15a and 15b in the memory cell transistor and patterned to form a source electrode 17a and a drain electrode 17b. Simultaneously, the polysilicon layer fills the contact holes 18a and 18b in correspondence to the peripheral region to form a source electrode 13a and a drain electrode 13b. Thereby, the flash-EPROM is shown is completed as indicated in FIG. 1(I).
In the foregoing process of fabrication, it should be noted that the photoresist 9 contacts directly with the capacitor insulation film 8 in the step of FIG. 1(F). Thereby, a problem arises in that the capacitor insulation film 8a is contaminated by the impurities released from the resist 9, and such impurity elements causes a degradation in the quality of the insulation film 8a. Such a degradation of the capacitor insulation film causes various problems such as leaking of accumulated electric charges, degradation of the dielectric strength of the film 9a, and the like. Thereby, the operation of the flash-EPROM becomes unstable. Further, the lifetime of the device for repeated writing of information is deteriorated.
In order to avoid the foregoing problem, an alternative method is proposed to eliminate the contact between the capacitor insulation film 8a and the photoresist 9 as shown in FIGS. 2(A)-2(F), wherein the step of FIG. 2(A) follows the step of FIG. 1(C).
Referring to FIG. 2(A), a photoresist layer is deposited on the structure of FIG. 1(C) and patterned subsequently to form a resist pattern 6.sub.1 that exposes the upper major surface of the polysilicon layer 6 in correspondence to the peripheral region. Further, while using the resist pattern 6.sub.1 as a mask, the polysilicon layer 6 is subjected to a reactive ion etching process such that the upper major surface of the substrate 1 is exposed in correspondence to the peripheral region. Thereby, the structure shown in FIG. 2(A) is obtained.
After the resist pattern 6.sub.1 is removed, the structure of FIG. 2(A) is subjected to a thermal oxidation process to form a silicon oxide layer 19a such that the layer 19a covers the upper major surface of the polysilicon layer 6. Simultaneously, a silicon oxide layer 19b is formed on the exposed upper major surface of the substrate 1 in correspondence to the peripheral region. Thereby, a structure shown in FIG. 2(B) is obtained.
Next, a resist layer 19.sub.11 is provided on the upper major surface of the silicon oxide layer 19a in correspondence to the memory cell region and an ion implantation process is conducted such that impurity elements are introduced into the substrate 1 in correspondence to the peripheral region via the silicon oxide layer 19b. Thereby, a channel region 20 is formed as indicated in FIG. 2(C).
Further, the resist layer 19.sub.11 is patterned in a step of FIG. 2(D) to form a resist pattern 19.sub.1 in correspondence to the floating gate electrode to be formed on the memory cell region. Further, by conducting a reactive ion etching process while using the resist pattern 19.sub.1 as a mask, the polysilicon layer 6 is patterned together with the silicon oxide layer 19a formed thereon to form the polysilicon electrode 6a as shown in FIG. 2(D).
Next, the resist pattern 19.sub.1 is removed in the step 2(E) and the silicon oxide film 19a on the patterned polysilicon electrode 6a is removed by the reactive ion etching process while protecting the silicon oxide film 19b on the peripheral region by another resist pattern 19.sub.2. After the resist pattern 19.sub.2 is removed and the polysilicon electrode 6a exposed, the structure of FIG. 2(E) is subjected to a thermal oxidation process to form a silicon oxide film 21a such that the film 21a covers the entirety of the electrode 6a as indicated in FIG. 2(F). Thereby, the electrode 6a forms the floating gate electrode.
After the step of FIG. 2(F), the process of FIG. 1(G) is conducted to cover the floating gate electrode 6a by the polysilicon layer 10. Further, by applying the processes already described with reference to FIGS. 1(H) and 1(I), one obtains the flash-EPROM as shown in FIG. 1(I).
In the foregoing alternative process, it will be noted that the polysilicon layer 10 covers the capacitor insulation film 6a directly and immediately when the film 6a is formed by the thermal oxidation process. Thereby, the problem of the photoresist contacting with the critical capacitor insulation film 6a is eliminated.
On the other hand, the foregoing alternative process has a problem in that there occurs a growth of the insulation film 19b in the step of FIG. 2(F). It should be noted that the insulation film 19b is formed in the oxidation step of FIG. 2(D), and the oxidation process achieved in the step of FIG. 2(F) increases the thickness of the film 19b. Thereby, the threshold voltage of the peripheral MOS transistor formed in the peripheral region tends to deviate from the desired value. It should be noted that the insulation film 19 acts as the gate insulation film of the peripheral MOS transistor and the variation in the thickness of the film 19b is critical to the threshold characteristics of the peripheral MOS transistor.